1. Technical Field
The present invention relates to electronic circuits, and in particular, to power consumption in electronic circuits.
2. Description of Related Art
As engineers seek ever increasing speeds in VLSI chips, complex problems continue to rise to the forefront. Power consumption in digital logic is dominated by clocks used to control and synchronize circuit operations across a logic domain or an electronic chip. The digital logic consists of circuit elements such as NAND and NOR logic gates and latches being used as clocked gates. VLSI technology continues to advance by increasing the number of circuit elements on VLSI chips and increasing the frequency at which these circuit elements are driven.
The frequency is increased further by reducing the number of logic gates between latches. These methods result in an increased amount of overall power consumption by these circuit elements and an even higher portion taken up by clocked gates. However, only a fraction of these clocked gates are, in any large design, on cycle time limiting paths.
Some prior art power consumption reduction mechanisms have primarily focused on logic reduction and logic gate sizing. However, selective reduction of clock power by substitution of clock gates addresses the main source of power consumption in state-of-the-art digital circuits.
Therefore, it would be advantageous to provide an active circuit that can reduce power consumption, such as is produced by high power consumption clocked gates, and it would be particularly advantageous to provide an active circuit to reduce power consumption by replacing those high power consumption clocked gates with lower power consumption clocked gates without affecting the target cycle time of the circuit.